Specifically, the present invention relates to a method for fabricating a memory device which has memory cells and devices for causing the memory cells to respond; trench structures are formed by microtechnology and can be filled with a crystallization agent which, after crystallization, has regions allowing ferroelectric storage of an item of information.
Ferroelectric data memories, also known as FeRAMs (FeRAM=FerroElectric Random Access Memory) are based on the ferroelectric effect. Ferroelectric materials are materials which have a spontaneous polarization which can be reversed in an electric field. A material which is preferably used in the ferroelectric storage capacitors is lead zirconate titanate (PZT, Pb(Zr, Ti) O3 for short).
Memory devices based on ferroelectric memory cells have the advantage of not requiring a refresh cycle, which for conventional memory cells based on electrical capacitors is typically 64 ms (milliseconds). The spontaneous polarization is retained even after the operating voltage has been switched off, which means that the information is stored in nonvolatile form and there is no need for a refresh cycle.
One drawback of modern conventional FeRAMs consists in the fact that the storage density which can be achieved is only low compared to dielectric data memories, such as for example DRAMs. A typical storage density for an FeRAM is, for example, 256 kBit. It is therefore important to increase the storage density of memory devices with PZT-based memory cells.
To solve this problem, DE 195 43 539 C1 proposes a method for fabricating a memory cell arrangement in which stacked capacitors with a ferroelectric or a paraelectric storage dielectric are used. According to the device disclosed in DE 195 43 539 C1, the stacked capacitors are designed as vertical storage capacitors. To fabricate a storage capacitor of this type, a dielectric layer is produced over the entire surface area for the storage dielectric. Then, the dielectric layer is patterned and first electrodes and second electrodes for the storage capacitors are formed. Select transistor pairs for corresponding memory cells which belong to adjacent word line pairs are arranged offset in the substrate in the customary way.